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11.5.16 CMU_IEN - Interrupt Enable Register
Offset
0x03C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5
CALRDY
0
RW
Calibration Ready Interrupt Enable
Set to enable the Calibration Ready Interrupt.
4
AUXHFRCORDY
0
RW
AUXHFRCO Ready Interrupt Enable
Set to enable the AUXHFRCO Ready Interrupt.
3
LFXORDY
0
RW
LFXO Ready Interrupt Enable
Set to enable the LFXO Ready Interrupt.
2
LFRCORDY
0
RW
LFRCO Ready Interrupt Enable
Set to enable the LFRCO Ready Interrupt.
1
HFXORDY
0
RW
HFXO Ready Interrupt Enable
Set to enable the HFXO Ready Interrupt.
0
HFRCORDY
0
RW
HFRCO Ready Interrupt Enable
Set to enable the HFRCO Ready Interrupt.
11.5.17 CMU_HFCORECLKEN0 - High Frequency Core Clock Enable
Register 0
Offset
0x040
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
3
EBI
0
RW
External Bus Interface Clock Enable
Set to enable the clock for EBI.
2
LE
0
RW
Low Energy Peripheral Interface Clock Enable
Set to enable the clock for LE. Interface used for bus access to Low Energy peripherals.
1
DMA
0
RW
Direct Memory Access Controller Clock Enable
Set to enable the clock for DMA.
0
AES
0
RW
Advanced Encryption Standard Accelerator Clock Enable
Set to enable the clock for AES.
2011-04-12 - d0001_Rev1.10
112
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